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-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to   
-- suit user's needs .Comments are provided in each section to help the user  
-- fill out necessary details.                                                
-- ***************************************************************************
-- Generated on "02/21/2016 20:20:09"
                                                            
-- Vhdl Test Bench template for design  :  BCD_COUNTER
-- 
-- Simulation tool : ModelSim-Altera (VHDL)
-- 

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY BCD_COUNTER_vhd_tst IS
END BCD_COUNTER_vhd_tst;
ARCHITECTURE BCD_COUNTER_arch OF BCD_COUNTER_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL i_count_carry_in : STD_LOGIC;
SIGNAL i_sys_clk : STD_LOGIC;
SIGNAL i_sys_rst : STD_LOGIC;
SIGNAL o_count : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL o_count_carry_out : STD_LOGIC;
COMPONENT BCD_COUNTER
	PORT (
	i_count_carry_in : IN STD_LOGIC;
	i_sys_clk : IN STD_LOGIC;
	i_sys_rst : IN STD_LOGIC;
	o_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	o_count_carry_out : OUT STD_LOGIC
	);
END COMPONENT;
BEGIN
	i1 : BCD_COUNTER
	PORT MAP (
-- list connections between master ports and signals
	i_count_carry_in => i_count_carry_in, 
	i_sys_clk=> i_sys_clk,
	i_sys_rst => i_sys_rst,
	o_count => o_count,
	o_count_carry_out => o_count_carry_out
	);
clk: PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
	  i_sys_clk<='1';    
     wait for 10ns;    
     i_sys_clk<='0';    
     wait for 10ns;                    
--WAIT;                                                       
END PROCESS ;                                           
tb : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
    i_count_carry_in <= '1';
	 i_sys_rst <= '1';
	 wait for 100ns;
	 i_sys_rst <= '0';
	 wait for 10ns;
	 -- code executes for every event on sensitivity list  
WAIT;                                                        
END PROCESS ;                                       
END BCD_COUNTER_arch;
